Shown in FIG. 1 is a prior art zero crossing detector circuit. The illustrated circuit consists of an open-collector comparator circuit which is configured in a difference amp configuration. The zero crossing detector circuit generates an output square wave from an input sinusoidal wave. For example, the input sinusoidal wave is delivered to V.sub.1, which imposes a voltage on the non-inverting input V.sub.+ via R.sub.1, and to V.sub.2, which imposes a voltage on the inverting input V.sub.- via voltage divider R.sub.2 /R.sub.5. When V.sub.+ is greater than V.sub.- the circuit output is HIGH (V.sub.cc), and when V.sub.+ is greater than V.sub.- the circuit output is LOW (the saturation voltage of the comparator). Most importantly, however, the circuit detects the point in time when the input voltage makes a transition from a higher value to a lower value--referenced to zero volts. However, because the inputs V.sub.+ and V.sub.- are imbalanced, the circuit does not satisfactorily detect when the input signal crosses zero.
The present invention is directed to overcoming one or more of the problems as set forth above.